# E07 native PCB → device asset contract

Prepared 2026-10-08. This is the build contract, not a successful final CAD/physical verification report. No KiCad export, browser or renderer was run while preparing these scripts.

## Commands after root freezes routing

Run from `/Users/dubick/ChatGPT/projects/server-bmc-panel`:

1. Complete panel ERC/DRC, schematic parity and netlist checks; write `verification/E07/panel-drc.json` with `_sourcePcbSha256` for the frozen board. A current DRC with no errors, no unconnected items and no parity violations is required. Warnings remain visible in metadata. A fresh internal-board DRC is written to verification/E07/internal-drc.json and must match the unchanged E05 source PCB. Both ERC reports also belong to verification/E07.
2. `/Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/Current/bin/python3 tools/e07/export_visuals.py --audit-only` checks the native metadata contract without creating GLB or boards.json.
3. On the root-coordinated export slot: `/Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/Current/bin/python3 tools/e07/export_visuals.py` exports the E07 panel and reuses the unchanged native E05 internal GLB only after matching its existing PCB, netlist and GLB hashes. Output: `exports/E07/visual/panel-e07.glb`, `internal-e05.glb`, `boards.json`, export logs.
4. `node web/device/build-e07-assets.mjs --geometry-only` checks the native board inside the device without assembly exports. Output: `verification/E07/device-geometry-audit.json`.
5. `node web/device/build-e07-assets.mjs` performs the same checks and, only if all hard checks pass, exports `exports/E07/device-E07.glb`, `device-E07-exploded.glb`, `device-E07-spec.json`, and `verification/E07/device-geometry.json`.
6. Root integrates those exact files in the viewer/release; one root-coordinated browser test follows. No E05/E06 artifact is overwritten.

Steps 4 and 5 repeat the same checks by design: use step 4 only when diagnosing geometry before final export. A successful final step 5 does not need another identical audit.

## Source and unit contract

`boards.json.revision` is E07. Panel board revision is E07, while the internal board remains E05 and has `assemblyRevision: E07`. Download names preserve native revision (`bmc_internal_e05.*`). Internal E05 is not regenerated.

The exporter verifies every numbered pad against its native XML netlist; schematic mechanical-only H201…H204 are handled separately. PCB/netlist hashes are checked before and after each native export. The E05 internal GLB is reused byte-for-byte so archived E05 metadata remains valid. It exports actual tracks, zones, pads, silkscreen and mask with DNP bodies omitted. Metadata includes exact PCB/netlist/GLB/DRC SHA256, copper-layer count, NPTH and via positions. `bodyBoundsPcbMm`, `position` and `size` remain explicitly approximate selection data; they are never used to prove component height or 3D collision.

Coordinates in GLB/metadata are metres with `(x,y,z)=(PCB X, height, PCB Y)` and origin `(0,0)`. Assembly applies a single uniform 1000 scale, rotation X=π/2, and translation `[-42,23,5.9]` millimetres. Thus native `(PCB X, height, PCB Y)` maps to `(X−42,23−Y,5.9+height)` in the device. Nothing is stretched to fit.

The builder validates current PCB, netlist, metadata, GLB and DRC hashes before attaching geometry and again before writing artifacts; model source dependencies are also hashed. Stale sources fail the build.

## Hard checks and remaining limits

Hard checks cover the 84×46×0.8 mm / six-layer board, four native Ø1.8 NPTH, assembly transform and placeholder removal, native component bodies by reference, nominal body height/cavity fit, battery reserve intersection, native via radius/pad centres in the battery keepout, stock LCD/CG maximum W/H envelopes, front-seat corner containment, AA centring and unchanged fixed USB/support movement. Actual component AABBs are measured from GLB nodes by reference; missing fitted component bodies fail instead of being replaced by boxes. Native pad-only testpoints, mounting holes, solder jumpers and explicit wire/SWD termination footprints do not require a body STEP.

Assembly geometry checks stop on a hard failure and do not overwrite a new assembly GLB with failed geometry. Existing prior artifacts, if any, must not be published as the new result: the current JSON report and source hashes are authoritative.

Explicitly unverified: supplier pin-1 convention/FPC reach and bends, display pin40/init, STEP versus actual maximum component tolerances, battery swelling/NTC/thermal/current tests, enclosure tolerance/strength, 2U rotation clearance, firmware, physical first article. These appear as `unverified`; `manufacturingReady` and `physicalTestsPerformed` remain false. In particular nominal KiCad STEP geometry is not a certified worst-case component envelope, and no digital CAD check proves a functioning board.


## Required release-report provenance (current contract)

`verification/E07/verification-E07.json` has `revision: E07`, a nonempty `sourceHashes` map of **project-relative canonical paths → lowercase 64-character SHA256**, and `boards.internal` / `boards.panel`. Each board contains `ercErrors`, `drcErrors`, `unconnectedItems`, `schematicParityIssues` equal to zero, plus `sourcePcbSha256` and `sourceNetlistSha256` matching native metadata. The map must include:

- `hardware/E05/internal/bmc_internal_e05.kicad_pcb`, `exports/E05/bmc_internal_e05.xml`;
- `hardware/E07/panel/bmc_panel_e07.kicad_pcb`, `exports/E07/bmc_panel_e07.xml`;
- `verification/E07/internal-drc.json`, `internal-erc.json`, `panel-drc.json`, `panel-erc.json` (all paths under `verification/E07/`);
- every direct `.kicad_sch` and `.kicad_pro` file in `hardware/E05/internal` and `hardware/E07/panel`;
- `tools/e07/verify_e07.py` and `tools/e07/panel_pcb.py`.

Any additional `sourceHashes` entries are verified too. `functional-countercheck.json` must contain the same map keys, plus hashes for `verification/E07/verification-E07.json`, `verification/E07/device-geometry.json` and its own generator `tools/e07/report_e07.py`. Generate final verification first, then native/geometry artifacts, then the functional audit. Do not add either report's own hash to itself. The functional audit is downstream, never an input to geometry or verification.

`boards.json` records `board.verification.sourceDrc` as `verification/E07/<internal|panel>-drc.json`. E05 describes the internal CAD revision, while its fresh review is part of E07.

The web build checks all source-map entries and required keys, all five geometry bindings (PCB, XML netlist, DRC, metadata JSON, native GLB), complete model dependency hashes, and assembly artifact hashes. It also compares staged copies to their source files so a source changing after copy cannot yield a ready manifest. Missing/stale provenance produces `status: incomplete`, never a ready release.